Experienced FPGA (VHDL) Designer, responsibility include:
- Oversees definition, design, verification, and documentation for FPGA development.
- Determines architecture design, logic design, and system simulation.
- Defines module interfaces/formats for simulation.
- Prepare detailed design documentation
- HDL coding, logical equivalency checking, static timing analysis, CDC, linting
- Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use.
- Integration of third-party IP
- Create self-checking and reusable test benches from scratch, utilizing Object Oriented Programming concepts: Inheritance, Polymorphism, etc.
- Develop Functional Coverage Models and closing Code Coverage
- Experience in scripting languages: Make, Perl, Python, shell scripts, etc.
- Experience in Revision Control Systems: Subversion (SVN), CVS, Git.
- Work experience writing architectural design documents (micro-architecture documents with timing diagrams, detailed design blocks, etc.).
- Work experience performing RTL synthesis.
- Work experience performing Static Timing Analysis and correcting timing violations.
- Work experience creating a self-checking simulation test benches from scratch.
- Familiar with Xilinx Vivado or Microsemi Libero