20 Apr
Principal/Senior Design Verification Engineer
Vacancy expired!
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Job Title: Principal/Senior Design Verification EngineerJob Location: Santa Clara, CA.Job Type: Fulltime Salary: Depends on the experience. We are looking for senior/principal Design Verification Engineers with proven experience in all aspects of verification in UVM from start to finish. The candidate must have experience using Verification IPs from 3rd party vendors and a good knowledge of communication protocols such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, etc. Basic qualifications:- Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Maser’s is
- ≥8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and
- Entrepreneurial, open-mind behavior and can-do Think and act fast with the customer in mind!
- Authorized to work in the US and start
- Hands-on in UVM, strong knowledge on UVM constructs (uvmcallback, uvmsequence, uvm phases)
- Must be able to work independently to develop test-plans, and related test-sequences exercising the right stimuli and work collaboratively with RTL designers to debug
- Develop user-controlled random constraints in transaction-based verification methodology. Experience writing assertions, cover properties.
- Must have prior experience using Verification IPs from 3rd party vendors for communication protocols such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB,
- Integrate Verification IPs to core design and build env layer on top of
- Strong familiarity with generating coverage using VCS, analyzing Coverage Data using tools like Synopsys DVE/Verdi.
- Understanding of management buses like I2C/JTAG.
- Working knowledge of running gate level simulation and SDF back annotation
- RTL design expertise is a plus, including asynchronous clock domain crossing and FIFO verification
- Physical Layer, Link Layer and Transaction Layer verification expertise in PCIe protocol
- Experience with FPGA-based verification/emulation
Vacancy expired!