RTL Design Engineer

Hi

• Digital Design Engineer to implement custom logic in ASIC for Facebook’s AR/VR products and in FPGA for prototyping and research.
• Areas of interests include Graphics, Audio or Compression.
• Primary language is SystemVerilog with some HLS where it is effective.

• Implement and deliver verified RTL blocks based on architectural and micro-architectural requirements.
• Contribute to the architectural and micro-architectural requirements.
• Support the Digital Verification, Physical Design, and Firmware teams to ensure correctness of the delivered RTL.
• Respond to issues found by engineers running the Lint, CDC, STA, Synthesis, and LEC tools.
• Support handoff of RTL blocks to prototyping engineers for integrating the delivered RTL into FPGA platforms.

• What are the top non-negotiable skill sets needed to be successful in this role?
• Experience with Verilog or SystemVerilog RTL coding for ASIC releases.
• Is this position eligible for remote work?
• MPK preferred, but Redmond is also open. Only these two locations.

• History of successful tape out of several ASIC releases using SystemVerilog RTL coding (Additional FPGA experience is a plus).
• Experience with closing timing and meeting power consumption goals in large designs in advanced technology nodes (sub-10nm geometries is a plus).
• Scripting language experience such as Python, Perl, TCL, etc. (Python is a plus).
• Debugging experience in simulation, emulation, and system bring-up in collaboration with Verification, Emulation, Physical Design, Firmware teams, etc.

• Bachelor's degree in Electrical or Computer Engineering, with 5 years of relevant ASIC digital design experience

• RTL DESIGN, Graphics, Audio, RTA, CDC