22 Apr
Staff Physical Design Engineer
Vacancy expired!
- Active participation in technical and schedule discussions with ASIC customers and design teams
- Chip/Block Level Floorplanning and pin assignment
- Pre-layout STA to ascertain feasibility, timing constraint validation and feedback to customers and design teams
- Review top-level/block-level clock specifications for completeness and feasibility
- Handle all the Physical design tasks (Placement, Timing Optimization, Clock Tree Synthesis, Routing)
- Perform sign-off tasks (RC Extraction, Static Timing Analysis, IR drop analysis and Physical Verification)
- Experience in ASIC Physical Design; Experience in an SoC product development organization with tapeouts at 28nm/16nm design nodes
- Experience with implementation EDA tools like ICC2/Innovus
- Experience in both Flat and Hierarchical layouts.
- Strong problem solving skills and ability to analyze and resolve physical design issues related to library, timing constraints or CAD tools is required.
- Experience with power analysis and IR-drop tools (primepower/Redhawk) and Static Timing Analysis (Primetime)
- Experience with Physical Verification and fix PV errors in layout
- Handling of Verilog HDL based Netlists, Physical design libraries, Scripting (Perl/Tcl/Python)
- Have an understanding of ASIC frontend design.
Vacancy expired!