14 Jun
Senior Physical Design Engineer
California, Santaclara , 95050 Santaclara USA

Vacancy expired!

OSITION SUMMARYResponsibilities:• Participate and Provide inputs for large networking chips Physical Design Methodology• Work on Blocks with IO, PLL and Efuse macros and take it through complete signoff• Work on closing final DRCs, manually or with scripts• Work on AP routing for complete chip• Manage chip level integration and physical verificationTechnical Skills required:Must have Skills:• MSEE/MSCS/MSCE degree or BSEE/BSCS/BSCE degree• Experience with advanced technology like 7nm, 5nm in terms of doing large chips physical design• Expertise developing flow for PD using synopsys/cadence tool chains• Expertise in signoff (timing, IR, EM, Verification) for tapeout quality GDS• Guide and manage PD team members• Participate in pre-sales activities• Work with teams across different locationsGood to have skills: • Scripting tools like Tcl, ShelleInfochips is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, sexual orientation, gender identity, national origin, veteran or disability status

Vacancy expired!


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