14 Jun
SENIOR VERIFICATION ENGINEER
Vacancy expired!
- Responsible for all aspects of verification methodology employed and for ensuring the application of uniform standards and adoption of best
- Work and liaison with other Design Verification teams within our customer sites to identify holes in the design verification flow and implement corrective
- Overall, responsible for verification of ASIC designs To include such things as:
- Design Verification – Implement test benches in UVM and Sytem Verilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug tracking and code coverage, debug failures and provide feedback to the design
- Responsible for oversight and completion of debugging problems and troubleshooting in Real Time. This includes being responsible for Debugging Designs for High throughput, Low Latency of Pipeline and Dynamic Power Management at full system level.
- Setup Verification Regression suites at RTL Level & Corresponding Netlist Level after Synthesis to test any/all Corner case
- Work closely with our design team to ensure the Company is meeting design requirements for projects. This may include: review of specifications, understanding chip architecture, developing tests & coverage plans, and defining methodology & test benches.
- Work closely with our Custom SoC department to provide great customer service to our clients and the projects at hand. Support, encourage and drive timely and accurate deliverables with customers within schedules
- 10+ years of industry experience bringing silicon ICs into high volume
- Must have good experience with UVM
- Must have a full chip verification experience
- Experience of leading a single project.
- Knowledge of industry standard interfaces. Familiarity with Verilog, Simulation tools & demonstrated ability to debug Problems & Troubleshoot in Real
- Knowledge of ARMv8, interconnect, memory coherence and memory architectures
- Familiarity with Formality & most popular Verification Tools. (Key knowledge should include such topics as: IP validation, Gate level verification, FPGA Validation, Emulation, Silicon Validation, Reference Board bring up verification, Silicon Bring up, DFx, Low Power Verification)
- Knowledge of ASIC design and verification flow including RTL design, simulation, test bench development, regression, equivalence checking, timing analysis, scan insertion and test pattern generation
- Functional understanding of constrained random verification process, functional coverage, and code
- Low power verification UPF
Vacancy expired!