25 Jul
California,
Sanjose
, 95101
Sanjose
USA
Vacancy expired!
ASIC RTL Design Engineer We have the below full time position with our client in San Jose. Pls send your resume with your salary expectation.KEY SKILLS- RTL Logic Design in multi-million gate ASICs with Verilog or System Verilog.
- Experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies
- Experience in writing specifications.
- Experience with multiple clock domains and asynchronous interfaces
- Knowledge of system architecture, CPU & IP integration, power and clock domains
- Familiarity with software and operating systems concepts
Have good experience in:- Computer Architecture concepts
- SoC system bfabric/interconnect design
- Memory controller design
- Integrate IP/sub-system
- Experience in Verilog is a must, System Verilog is a plus
- Should have knowledge of AMBA protocols - AXI, AHB, APB and other Management interfaces.
- Networking packet based bus protocols
- Timing closure at high frequencies is a plus
- Familiarity with scripting languages such as Perl, Python
DESCRIPTION:As a member of the SoC Design team, you will be responsible for the following: Microarchitecture and design high-performance (low-latency, high-bandwidth, high-frequency), low-power on-chip fabric/interconnect and fabric components, Analyze and configure fabric components to meet topology, bandwidth and latency needs of SoC Integrate fabric components at SoC level and sub-system level, including instantiation, connectivity, perform structural checks (such as Lint, CDC)) Synthesis and timing closure Power analysis of design components (using industry standard tools) Optimize design components for power and performance Develop and maintain methodology/flows/checks for designs Work with multi-disciplinary groups to deliver designs on time with the highest quality.
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