03 Aug
California,
Cupertino
, 95014
Cupertino
USA
Vacancy expired!
START: August/September MUST HAVES: 1: RF/RFIC 2: 28nm 3: Cadence Virtuoso 4: Block experience (ADC/DAC/PLL) 5: EE Degree or Masters in EE DOES NOT WANT TO SEE: 1) Typos/sloppy resumes 2) A lot or recent DIGITAL experience (it is unrelated to their Analog/RF needs) 3) Short term 3-6 month assignments on their resume. DESCRIPTION Key Qualifications - Positions are available for multiple experience levels.
- We want you to have experience in custom analog layout from floorplan, placement, routing, and verification, with extensive experience on deep sub-micron CMOS (16nm, 7nm, etc.). mmWave experience is a plus.
- Knowledge in FinFet device structures, guard-rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, and DFM etc. will be critical to your success.
- Understanding of trade-offs in matching, parasitic effects, high frequency routing, isolation, coupling, shielding, RC delay, EM, IR, ESD and latch-up is key.
- Working knowledge of Cadence Virtuoso and Mentor Calibre, and proficiency in interpreting verification results of DRC, LVS, ERC, and ANT are skills you need to succeed.
- We would welcome a great teammate with excellent communication skills to work with multi-functional teams.
- Please be prepared to proactively work with circuit designers for optimal solutions to problems, and recognize failure prone circuit and layout structures.
- You can benefit from the ability to provide accurate schedule and update plans to meet project milestones.
- Knowledge of Totem, EM/IR tools, PAD/EAD and constraint editor experience would be a plus.
- Experience with Skill, Python, Perl, layout scripts for automation and improvement of flow will be helpful.
Description We expect you to perform: - Detailed transistor level layout of analog and RF circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO. - Layout of sensitive analog components including resistors, capacitors, and inductors. - Block level and top-level layout through full verification flow including extraction, DRC, LVS, and DFM. - Collaborate with designers on block level placement and top-level floor planning. - Layout review for power/ground routing, electro-migration, power distribution, signal path, differential and IQ matching, and signal coupling. - Top-level layout integration, verification, and project schedule management. Education & Experience BSEE or equivalent would set you up for success in this role. #Dice-SPG #Mon-SPG #Zip-SPG #CB-SPGYoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Visit https://www.yoh.com/applicants-with-disabilities to contact us if you are an individual with a disability and require accommodation in the application process.
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