ASIC Design Engineer Needed / San Diego / Hybrid RemoteThis Jobot Job is hosted by: Kevin SzilagyiAre you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume.Salary: $130,000 - $190,000 per yearA bit about us:If you are an high level RF ASIC Design engineer this opportunity is for you. Based in San Diego the company performs cutting-edge research in smartphone technologies, including but not limited to communications, computer vision, and video and image processing. With a staff comprised of talented scientists and engineers, the company delivers designs, algorithms and products that provide a positive impact on end users' daily interactions with technology, whether it be with smart devices, communication networks, or services in the cloud.Why join us?
Job DetailsRequired skills/tools:
- Amazing work culture
- Competitive base salary
- Hybrid remote
- Great Benefits Package
- Hands on experience with ASIC/FPGA design, verification or related work knowledge.
- RTL design with Verilog, System Verilog or VHDL. FPGA design using Quartus or Vivado.
- Familiarity with front-end, middle-end, and back-end ASIC design tools
Responsibilities:In a multi-site project team, you are working on the design and implementation of the custom ASIC design and integration of such blocks into high performance RF radios for cellular (4G/5G) and Connectivity (WiFi/Bluetooth/GNSS):Top/Block level RTL (Verilog or System Verilog) design, integration and test.Work with RF/Analog IC design teams to implement calibration algorithms and control functions (in Verilog) for analog circuits such as ADC & DAC, Phase Lock Loops (PLLs).Design and implement Digital Signal Processing functions for digital receivers and transmitters such as FIR filters and Gain Control.Design and implement microprocessors/memories/peripheral control.Work with Test Teams to verify digital and analog radio functionality.Develop FPGA Designs (Altera/Xilinx) for radio test & prototype platforms.Optimize ASIC for power, performance, area and timing.Participate in Physical Design of ASICs: Synthesize, Scan Insertion, ATPG, Floor Planning, Place and Route, Timing Closure, Formal Verification, Static Timing Analysis, Back Annotation Sims.
- Familiarity with lab equipment (Logic Analyzers, Oscilloscopes, Spectrum Analyzers).
Interested in hearing more? Easy Apply now by clicking the "Apply Now" button.
- Experience with scripting tools such as Perl, Matlab.
- Knowledge of radio transceivers, digital signal processing, and microprocessors.
- Proven track record of completing complex designs on time.