FPGA Verification Engineer

Reference # : 20-00848

Title : FPGA Verification Engineer

Category: Information TechnologyLocation : Bloomington, MNPosition Type : Right to Hire

Experience Level : 2 Years

Start Date : 04/09/2020Description Job Title: FPGA Verification EngineerLocation: Bloomington, MinnesotaJob Description: Our client, a large defense contractor, has an immediate opening for a FPGA Verification Engineer to work from their Bloomington, Minnesota facility. They are seeking an experienced FPGA Verification Engineer who possess functional verification experience utilizing Object Orientated programming (C, C#, C+), familiarity with Universal Verification Methodologies (UVM), System Verilog, assertions checking and constrained random stimulus. The FPGA Verification Engineer position requires a Bachelor's degree in Electrical Engineering and relevant work experience with FPGA SystemVerilog constrained random Digital LogicVerification techniques, methodologies and related verification activities.Qualifications: Bachelor's degree in Electrical or Computer Engineering, a related specialized area or field is required (or equivalent experience) plus a minimum of 2 years of relevant experience; or Master's degree. Department of Defense security clearance is not required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.Successful candidate attributes:

Experience writing object orientated programming code such as C, C#, C+

Contributed to verification plans, UVM testbenches, System Verilog assertions, and functional coverage models to support coverage-driven verification

Experience with functional verification methodologies to meet functional and code coverage goals

Has used and developed constrained random behavioral register transfer level (RTL) simulations

Has experience with Mentor QuestaSim and Mentor Graphics Verification IP (QVIP)

Familiar with Verilog/System Verilog

Familiar with requirement decomposition

Basic understanding of Hardware Logic Types

Basic understanding of Computer Architecture

Direct Programming Interface (DPI) experience

Linux, Jenkins and various other scripting approaches

Familiar with PCIe, Gigabit Ethernet, Fibre Channel and embedded microprocessor verification techniques

Occasional travel may be required.Equal Opportunity Employer Veterans/Disabled.