R&D Engineer

Description:Looking for experienced engineers in the areas of SW Modeling of Hardware, C/Assembly Test, and CAD/CAE tooling.Job Description: The candidate will be responsible for definition, implementation, debug, and maintenance of CPU architecture verification test suites utilizing extensive Assembly and C level code and interfacing into a System Verilog simulation environment. This person must interface with designers and micro-architects for ensuring coverage goals are established and realized. Test design will span multiple levels of system hierarchy running on a custom 64-bit RISC supercomputer.The candidate will be writing assembly/C code using the processor ISA (Instruction Set Architecture) to verify the design.