Design Verification Engineer
Vacancy expired!
Design Verification Engineer Apex systems the 2 nd largest staffing firm in the nation is currently seeking a design Verification to join our client's team. This position is located in Redmond, WA or Menlo Park, CA, and is a great opportunity to advance your technical career with an industry leader! Please send all qualified resumes to Joe Measell (Network/Infrastructure Recruiter) at Key Details of the Design Verification Engineer: Location: Redmond, WA or Menlo Park, CA Duration: 12 months Core Functions: Design Verification Technologies: UVM, ICs, C Additional: As a Contractor, you'll receive weekly pay, PTO, healthcare benefits, 401K program, ESPP (employee stock purchase program), virtual training program, access to technical training license with cert boot camps for 120+ IT certifications, and more Responsibilities of the Design Verification Engineer:
- Write and augment existing testplans.
- Implement testbench and scoreboards / checkers.
- Implement test sequences as per plan and debug failures
- Achieve 100% functional and code coverage
- Work closely with designers, micro architects & f/w to resolve issues
- Ability to communicate & articulate clearly progress / issues with project leads
- 5+ years of proven experience as a DV engineer
- Implied: Candidate will have hands on Experience with executable test plans and Coverage Driven verification
- 2+ years of hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)
- Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
- Scripting (python, perl or similar)
- SoC level design verification experience
- ASIC design experience
- Experience in Computer Graphics & Display Subsystems is desirable
Vacancy expired!