Senior ASIC Design Verification Engineer

Job Description

At Palo Alto Networks® everything starts and ends with our mission: protecting our way of life in the digital age by preventing successful cyberattacks. It’s not a small goal. It isn’t simple either, but we aren’t in this for the easy answer. As a company with a foundation in challenging the way things are done, we’re looking for innovators with a dedication to best. In return, your career will have a tangible impact – one that's working toward technology that affects every level of society.

Our mission doesn’t happen by treading softly – no, it happens by defining an industry. It means building products that haven't been thought of. It means selling products with a solutions mindset. It means supporting the infrastructure of a company that moves at an incredible speed – intentionally – to stay ahead of the world’s next cyberthreat.

We are the global cybersecurity leader, known for always challenging the security status quo. Our mission is to protect our way of life in the digital age by preventing successful cyberattacks. This has given us the privilege of safely enabling tens of thousands of organizations and their customers. Our pioneering Security Operating Platform emboldens their digital transformation with continuous innovation that seizes the latest breakthroughs in security, automation, and analytics. By delivering a true platform and empowering a growing ecosystem of change-makers like us, we provide highly effective and innovative cybersecurity across clouds, networks, and mobile devices.

Our Security Operating Platform is built for automation. It is easy to operate, with capabilities that work together, so customers can prevent successful cyberattacks. They can use analytics to automate routine tasks, so they can focus on what matters. We are known for continuously delivering innovations; and with Application Framework, we extend that to an open ecosystem of developers that benefit from our customers’ existing investment in data, sensors, and enforcement points.

We’re trailblazers that dream big, take risks, and challenge cybersecurity’s status quo. It’s simple: we can’t accomplish our mission without diverse teams innovating, together. To learn more about our dedication to inclusion and innovation, visit ourLife at Palo Alto Networks pageand ourdiversitywebsite.

Palo Alto Networks is an equal opportunity employer. We celebrate diversity in our workplace, and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or other legally protected characteristics.

Additionally, we are committed to providing reasonable accommodations for all qualified individuals with a disability. If you require assistance or an accommodation due to a disability or special need, please contact us at[emailprotected].

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Qualifications

• Hands-on implementation work on every aspect of ASIC verification, working closely with the system group, architects, RTL designers and verification teams
• Developing the verification flow and methodology, test bench and test cases, plus executing the test plan, working closely with the design team to ensure the highest design quality
• Debugging test failures at block, full chip, and system level
• Evaluating and enhancing test plans to increase test coverage

• Minimum of 5 years of ASIC design verification experience with a proven track record of successfully verifying and delivering complex ASICs. Experience in going through several complete and successful ASIC design/verification cycles from architecting and creation of test environment to tape-out and post-silicon validation is required
• Solid technical skills in the area of design verification: planning, problem solving, debugging, random testing, adversarial testing required with a proven track record in the following areas of DV required:
• Test bench design and implementation
• Test plan definition
• Constrained random test development
• Coverage specification and analysis
• Reference model design and implementation
• Automation of the regression test suite
• Solid experience with UVM required
• Strong object-oriented software design and programming skills in C/C required
• Strong scripting skills in Python/Perl required
• Strong written and verbal communication/interpersonal skills required
• Experience in Lab bringup/debug is highly desirable
• Experience in formal verification is highly desirable
• Networking experience highly desirable

Additional Information

All your information will be kept confidential according to EEO guidelines.