Applications and Support Engineer Reliability Verification (Design Enablement)
Job DescriptionAt Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DE cross teams to ensure design-kits leadership for customer enablement for cutting edge technologies. You will also work with customers to outline critical requirements, collaborate with Intel internal partners to define the scope, plan execution, innovate competitive solutions to meets customer needs.This support role drives the solutions for Reliability tools/flows support when customers use intel PDK collaterals in their Design. You will lead the collaboration and communication across TD/DE organizations to find the best path to resolve the issue. Tasks also include owning/maintaining training documents, user guide, and customer ticket support.As a DEAS (Design Enablement Application and Support) key member, you will utilize consistent communication skills to interact with customers directly, apply analytical problem-solving capability to identify the key requests, root-causing the issue, and teamwork collaboration with DE stakeholders to support and enable customer success.This is an entry level position and compensated accordingly.#DesignEnablement.QualificationsYou must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.Minimum Qualifications:Candidate will have a MS degree with 6+ months of experience in Computer Engineering or Electrical Engineering or Computer Science or related STEM degree.6+ months of experience in the following:
Unix/Linux operating system.
With at least one of the following: C, or Python, or Perl, or TCL
Preferred Qualifications:6+ months of experience in the following:
Familiarity with VLSI design process and exposure to PDK and EDA tools (Synopsys ICV, Siemens/Mentor Calibre, and Cadence Pegasus, and CDNS Innovus/SNPS RM
Experience with working in software repository management tools like Git.
Knowledge in semiconductor device physics, models, parasitic extraction, reliability verification and technology scaling.
Inside this Business GroupAs the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.Other LocationsUS, AZ, Phoenix; US, CA, Santa ClaraPosting StatementAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)Annual Salary Range for jobs which could be performed in US, California: $91,500.00-$137,436.00Salary range dependent on a number of factors including location and experienceWorking ModelThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.